Sr. Staff Engineer, Front-End Verification

Required

• Front-End Experience: Solid background verifying CPU front-end blocks—such as instruction fetch, branch predictors (BTB, TAGE, RAS), instruction caches/TLBs, or decode—using SystemVerilog, UVM, and C++.
• Unit-Level Focus: Hands-on experience building clean, controllable unit testbench environments with precise stimulus and checking.
• Reusable Design: Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels.
• Collaborative Problem Solver: Comfortable working alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs.
• Unit-Level Verification: Work within the front-end DV team to build and maintain UVM testbenches for instruction fetch units, branch predictors, and related sub-blocks.
• Stimulus Generation: Develop constrained-random and directed tests targeting speculation depth, misprediction/redirect flows, fetch bubbles, and cache/TLB interactions.
• C++ Integration: Help develop and maintain C++ reference models and predictors that integrate into the verification framework for cycle-accurate or transaction-level checking.
• Execution & Closure: Execute verification plans, track functional and code coverage metrics, and ensure edge cases are verified.
• What You Will Learn
• RISC-V Front-End Microarchitecture: Practical experience with high-performance RISC-V fetch pipelines and prediction structures.
• Maintainable DV Infrastructure: Strategies for writing unit testbenches that remain manageable as designs evolve.
• Tooling & Workflows: Experience using both industry-standard simulators and open-source flows (e.g., Verilator) across simulation and emulation environments.