Develop and qualify wafer back-grinding, thinning, stress-relief, and backside finishing processes; set thickness, TTV, bow, warp, and roughness targets while minimizing chipping, cracking, subsurface damage, and edge defects

Develop and optimize mechanical wafer dicing (including thin wafers and difficult materials such as SiC); select blades, tapes, and parameters (speed, feed, depth, coolant, dressing, single- or multi-pass) and control chipping, sidewall quality, delamination, and street/exclusion requirements

Establish post-dice die cleaning, drying, handling, tape mount/release (UV and non-UV), pick, sort, and presentation methods that protect die integrity, orientation, and traceability for flip-chip, wire-bond, and other assembly flows

Develop and qualify laser marking processes for wafers and bare die (including green/UV sources); optimize mark contrast and resolution while avoiding damage to electrical performance, metallization, passivation, or mechanical integrity, and implement vision/OCR verification

Develop final package singulation (saw, laser, or mechanical) for organic, mold, ceramic, and metal structures; minimize cracking, chipping, delamination, burrs, and edge defects and confirm impact on warpage, electrical performance, and reliability

Run DOEs, define process windows and controls, troubleshoot defects, qualify equipment and consumables, incorporate supplier and production feedback, and transfer robust processes into manufacturing

Process Engineer, Wafer Preparation & Assembly (Starlink/Akoustis)

Responsibilities

Qualification

Required

Preferred

Benefits

Company

SpaceX

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