Senior Staff Engineer, Layout Design

SSI San Jose full timeOn Site

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senior

$189k–$301k

H1B: yes

Samsung Semiconductor Senior Staff Engineer leads verification for IP blocks of an AI accelerator, developing verification infrastructure and automation environments. Collaborates cross-functionally to debug failures and mentor junior engineers.

Responsibilities

Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
Mentor junior engineers when necessary
Work cross-functionally in debugging failures with design, compiler and simulation engineers
Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD's with 10+ years of industry experience.
Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
Understanding RTL and strong overall debugging skills
Prior experience with computational logic, interconnect networks and/or memory system is desirable
Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators

Qualification

Bachelor’s with 15+ years

Required

Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD with 10+ years of industry experience
Strong background in SoC or IP verification and test bench development