CPU Static Timing Analysis (STA)

Required

• Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in static timing analysis on high-speed designs.
• Knowledge in industry-standard EDA tools and scripting languages.
• Understanding various timing and noise analysis checks and corresponding constraints.
• Strong communication and collaboration skills.
• Possess substantial years of experience in CPU unit-level timing and noise analysis
• Understanding of timing noise models and hierarchical analysis strategies..
• Understanding of advanced technologies and scaling trends.
• Knowledge of physical design flow and methodology including logic synthesis, PnR, parasitic extraction, logic equivalence etc., which are related to timing analysis.
• Proficient in Python, Perl, or TCL to enhance design productivity and flow efficiency
• Experience in using Agentic AI tools for productivity and automation.
• The next great CPU won't build itself. We’re assembling a world-class team across every layer of CPU development, from architecture and design to verification, physical implementation, software, infrastructure, and product delivery. Every discipline matters, and every person has the opportunity to help shape the technology from the ground up.