Astera Labs is redefining the connectivity fabric that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer, you will own the backend implementation of complex, high-performance SoCs that sit at the heart of the world's largest AI clusters — driving floorplan, timing, power, and signoff decisions that directly determine product PPA and time-to-market.

This is a hands-on technical leadership role. You will architect physical design methodology, mentor senior engineers, and partner closely with RTL, DFT, analog, and package teams to take our next generation of connectivity silicon from RTL to tapeout on leading-edge nodes.

End-to-End RTL2GDS Ownership

Own the full RTL2GDS flow on advanced process nodes — synthesis, floorplan, placement, CTS, routing, and signoff — across Astera's connectivity product portfolio

Drive block- and chip-level place & route strategy, congestion resolution, and routing convergence on high-frequency, high-density designs

Architect clock tree synthesis and clocking topology to meet skew, latency, and power targets

Lead tapeout execution: final ECO closure, GDS handoff, and post-tapeout support through fab

Timing, Power & Signoff

Drive multi-mode multi-corner STA closure, low-power implementation (UPF/CPF), and IR/EM analysis to signoff

Own physical verification (LVS, DRC, antenna, ERC) and reliability signoff through clean closure

Define methodology for ECO flows, hierarchical timing, and full-chip signoff sign-around

Technical Leadership & Cross-Functional Partnership

Physical Design/CAD Engineer

Responsibilities

Qualification

Required

Preferred

Company

Astera Labs

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