Principal Physical Design Engineer, STA

San Josefull time

On Site

senior

H1B: yes

Astera Labs Principal Physical Design Engineer (STA) at Astera Labs responsible for timing closure and sign-off of connectivity ASICs. Collaborates with RTL, physical design, and verification teams to ensure robust full-chip timing convergence.

Responsibilities

Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.
Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.
Define and manage I/O timing budgets across hierarchical designs.
Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.
Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.
Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.
Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.

Qualification

Expertise in timing constraintsStrong knowledge of synthesisStrong scripting ability (TclKnowledge of ECO methodologiesSystemVerilog/Verilog familiarityThe base salary range is USD 209

Required

Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.
Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.
Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
Strong scripting ability (Tcl, Python, Perl).
Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred

Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
Experience working with IP vendors for both RTL and hard-macro integration.
SystemVerilog/Verilog familiarity.
The base salary range is USD 209,000.00 USD – USD 250,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Company

Astera Labs

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Source: greenhouse

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STAtiming closureSDC constraintsMMMC setupOCVAOCV

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Principal Physical Design Engineer, STA at Astera Labs · LumiJobs