Tenstorrent DFT Engineer at Tenstorrent responsible for implementing and integrating DFT features from RTL to tapeout for AI/ML architectures. Collaborate with cross-functional teams to optimize test coverage and reduce test costs.
Responsibilities
This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Qualification
Own ATPGPlanWhat You Will Learn
Required
You have a BS/MS/PhD in EE/ECE/CE/CS with 5+ years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs.
You are fluent in Verilog RTL for DFT logic (lock-up latches, clock gates, scan anchors) and comfortable with SystemVerilog/UVM.
You have hands-on experience with ATPG and DFx insertion tools, fault models (Stuck-at, Transition, Path Delay, IDDQ, Cell-Aware), and low-power design flows.
You bring strong debug and problem-solving skills across design hierarchies and collaborate effectively with design, PD, verification, and test teams.
Implement and integrate DFT features (scan, JTAG, compression, ASST, MBIST) into RTL from early design through tapeout across multiple IPs.
Own ATPG, test coverage analysis, and gate-level simulation (e.g., with Synopsys VCS/Verdi) to achieve and maintain high-quality test coverage.
Plan, implement, and verify MBIST, and work closely with Test Engineering on test planning, pattern delivery, and debug.
Develop and refine DFx flows and methodology that integrate cleanly with front-end and physical design flows, balancing coverage, test cost, and design intrusiveness.
What You Will Learn
How to drive DFT for industry-leading AI/ML architectures, working on high-performance chips with aggressive performance and power targets.
Practical strategies to reduce test cost while maintaining coverage, and to design DFT hooks that accelerate silicon bring-up and yield learning.
How to minimize DFT intrusions while integrating cleanly with RTL, verification, physical design, and production test flows.
