Top Level Physical Design Engineer

Required

• A seasoned physical design engineer who thrives on complex, full-chip implementation challenges.
• Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams.
• Passionate about optimizing chip-level implementations for power, performance, and area.
• Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules.
• 8+ years of top-level SOC physical design experience on complex, multi-million gate designs.
• Deep expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution.
• Proven track record with bump planning, RDL implementation, and multi-voltage domain designs.
• Mastery of timing closure, EM/IR analysis, and physical verification at the chip level.
• What You Will Learn
• How to implement cutting-edge AI accelerators and high-performance CPUs at the SOC level.
• Advanced techniques for chiplet integration and next-generation packaging co-design.
• Strategies for optimizing massive designs with complex power domains and clock architectures.