Silicon Power & Characterization Lead

Required

• A Principal-level engineer with 8+ years in silicon power analysis and characterization, and a Master’s or PhD in EE, CE, or related field.
• Deep understanding of digital and mixed-signal power domains, including DVFS, leakage vs. dynamic power, and power gating.
• Highly proficient in lab-based power measurement using oscilloscopes, current probes, power analyzers, and SMUs, plus Python/Perl/MATLAB for automation and analytics.
• A strong debugger and collaborator, comfortable driving cross-functional investigations and clearly communicating technical findings.
• Own the post-silicon power measurement strategy end-to-end across operating modes, voltages, frequencies, and workloads.
• Build and maintain lab infrastructure, automated workflows, and data analysis pipelines for high-fidelity, repeatable power characterization.
• Correlate silicon power data to pre-silicon models (RTL, gate-level, sign-off), drive root-cause analysis, and refine power estimation methodologies with design and modeling teams.
• Characterize power across PVT corners and work with bring-up/validation teams to develop test content, debug power anomalies, and ensure products meet power and performance specs.
• What you will learn
• How state-of-the-art SoCs behave in real silicon across diverse workloads, system configurations, and operating conditions.
• How to influence power architecture, RTL design, and modeling flows by feeding silicon insights directly back into early design phases.
• Best practices for building scalable, automated post-silicon power infrastructures that support multiple products and generations.