Risc-V Architect

Required

• Experienced Microarchitect: 10+ years of deep expertise in CPU performance modeling and microarchitecture design.
• AI Workload Expert: Deeply familiar with the computational and memory bottlenecks of modern AI workloads, particularly Large Language Models (LLMs).
• Hardware-Software Co-Designer: Driven to architect custom instruction set extensions and validate their performance gains against real-world workloads.
• Ways to stand-out: Familiarity with open-source RISC-V cores, AI-based agentic workflow experience
• Profile & Analyze: Dissect cutting-edge AI workloads to identify execution bottlenecks and translate those insights into definitive CPU performance requirements.
• Architect High-Performance Cores: Drive the microarchitecture of custom RISC-V CPU cores, balancing aggressive Performance, Power, and Area (PPA) targets.
• Innovate the ISA: Design and implement custom instructions that unlock massive performance gains without sacrificing compiler programmability or developer velocity.
• Cross-Functional Collaboration: Partner tightly across compiler, software, and hardware teams to co-design Tenstorrent’s next-generation AI compute architecture.
• What You Will Learn
• How modern AI models stress CPU architecture and influence design decisions.
• The interplay between compiler design, CPU microarchitecture, and real-world performance.
• How Tenstorrent’s unified hardware-software stack enables breakthrough performance for general-purpose AI compute.