Sr. Engineer, RTL Implementation

Required

• An expert in physical design practices used to optimize PPA
• Experienced in high-performance physical design.
• Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis.
• Skilled in synthesis, place and route tools including flows and physical design methodology.
• Background in CPU micro-architecture.
• Own front‐end physical implementation and PPA definition for a high‐performance RISC‐V CPU and CPU subsystem
• Work closely with microarchitects and RTL designers to “make the IP better” by optimizing frequency, power, and area across process nodes
• Define initial floorplans and early area, power, and frequency estimates for key CPU and subsystem configurations
• Partner with the broader PD organization and PD leads to improve and standardize methodologies, flows, and customer collateral for CPU, subsystem, and system IPs, acting as a “PD for IP” specialist bridging PD and design teams
• Use innovative techniques to optimize power, performance, and area while driving physical design experiments and evaluating results.
• Summarize and communicate PPA trade‐offs and recommendations to the broader RISC‐V and PD teams
• What You Will Learn