Chiplet Physical Design Engineer

Required

• An experienced physical design engineer with at least 10 years of relevant experience, who thrives in complex, multi-stakeholder projects.
• Detail-driven, with a strong sense of ownership from synthesis through design closure.
• Comfortable working at advanced nodes (3nm and below) and multi-GHz designs.
• A collaborative team player who enjoys mentoring others and influencing methodology.
• Clear communicator who can balance technical depth with schedule and resource constraints.
• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• 10+ years of industry experience in physical design for CPU, or GPU products.
• Strong hands-on experience with Synopsys and/or Cadence tools across synthesis, P&R, and closure.
• Proven expertise in timing closure, ECO flows, and PV convergence at block and chip level.
• Proficiency in scripting (TCL required; Python or similar strongly preferred) and strong English communication skills.
• What You Will Learn
• How large-scale chiplet-based systems are architected, implemented, and integrated into SiP solutions.