Tenstorrent Verification Lead role at Tenstorrent guiding a team of Verification Engineers to validate AI hardware functionality and performance. Focus on AI-specific data types, on-chip network validation, and leadership in verification strategy.
Responsibilities
Guide a top-tier team of Verification Engineers
Shape test strategies to validate functionality and performance of AI core
Architect verification plans for mixed-precision data types
Validate accuracy of complex AI transformations
Benchmark on-chip networks under high-demand traffic
Implement robust concurrency controls and multi-core synchronization
Develop portable test strategies scalable from subsystem simulations to FPGA and Silicon
Collaborate between hardware architecture and software requirements
Qualification
A Seasoned Verification LeaderAn AI Hardware SpecialistA Systems Architect at HeartA Technical MentorStrategic AI VerificationHigh-Performance NoC ExpertiseResiliency & Error InjectionPlatform-Agnostic MethodologyCross-Functional SynergyWhat You Will LearnNext-Gen AI/ML ToolingEvolving Workload Dynamics
Required
A Seasoned Verification Leader: An experienced ASIC/SoC lead with proven track record of leading teams through complex tape-outs.
An AI Hardware Specialist: An expert in the nuances of high-performance compute, specifically focused on AI/ML architectures and the intricacies of tensor-based operations.
A Systems Architect at Heart: A strategist who views verification through a system-level lens, ensuring that hardware, software, and on-chip networks (NoC) harmonize perfectly.
A Technical Mentor: A hands-on guide proficient in UVM, SystemVerilog, and cocotb, dedicated to elevating team capabilities and driving rigorous coverage-driven methodologies.
Strategic AI Verification: Expertise in architecting verification plans for mixed-precision data types (FP8, BF16, INT8) and validating the accuracy of complex AI transformations.
High-Performance NoC Expertise: Deep experience benchmarking on-chip networks under high-demand traffic, ensuring throughput, bandwidth, and congestion management meet peak requirements.
Resiliency & Error Injection: A proactive approach to system stability, implementing robust concurrency controls and multi-core synchronization to handle edge-case failures.
Platform-Agnostic Methodology: The ability to develop portable test strategies that scale seamlessly from subsystem-level simulations to FPGA and final Silicon.
Cross-Functional Synergy: A collaborative mindset that bridges the gap between hardware architecture and software requirements to ensure performance targets are met.
What You Will Learn
Next-Gen AI/ML Tooling: Integrating your specific advanced automation frameworks and emerging AI-driven verification techniques into the existing lifecycle.
Evolving Workload Dynamics: Gaining a deeper understanding of your proprietary AI workloads and how they stress memory access patterns uniquely within your architecture.